This invention relates generally to semiconductor fabrication processes, and more particularly to a method for planarizing integrated circuit surfaces where isolation trenches are used.
An area of a semiconductor substrate where a device or a part of a device is formed is referred to as an active area. For the device to exhibit desired characteristics, the active areas of respective devices are to be isolated. Isolation of devices typically is achieved by using local oxidation techniques or trench isolation techniques. Local oxidation techniques employ a thick film of oxidation material serving as a barrier between active areas. In trench isolation techniques a trench is formed between active areas of adjacent devices. The trench is filled with a dielectric or oxide material. An advantage of trench isolation is the avoidance of topographical irregularities typically encountered using local oxidation techniques. A difficulty of local oxidation is the encroachment of the oxide into the active areas, referred to in the art as bird's beak effect. Using trench isolation techniques, increased packing density and higher speed devices are achievable.
In forming isolation trenches deposition of a dielectric and subsequent polishing can result in a very irregular surface. If the irregularity is excessive, anomalous device leakage, reduced isolation integrity and subsequent metallization defects can occur. As this irregularity can be magnified during subsequent fabrication processes, it is important that the substrate and isolation trenches be as planar as possible.
Various types of isolation trenches are known in the art. Deep narrow trenches are used to isolate one device from another. Shallow trenches are used to isolate individual elements within a device (e.g., to isolate a drain from a source in a MOSFET). Wide trenches are used in areas where metallization patterns are to be deposited. Shallow, deep and wide trenches can be used interchangeably to isolate devices and parts thereof. These trenches are filled with dielectric materials such as silicon dioxide or silicon nitride using conformal deposition processes (e.g., chemical vapor deposition).
Isolation trench techniques include a planarization process which removes dielectric materials from the active areas while maintaining the dielectric materials in the trenches. While a narrow trench and closely packed trenches may be relatively easy to planarize, a wide trench or sparsely packed trenches may be more difficult. In particular, a process used to planarize a narrow trench may remove much of the dielectric from the wider trench. Because of the differing width of trenches, uniform planarization is difficult to achieve. Accordingly, there is a need for an isolation trench fabrication process which achieves uniform planarization.